ST10F296 datasheet(47/346 Pages) STMICROELECTRONICS

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ST10F296E

Internal Flash memory

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4LOCK

Flash registers access locked

When this bit is set, access to the Flash control registers

FCR0H/L-FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by

the FPEC. Any read access to the registers outputs invalid data

(software trap 009Bh) and any write access is ineffective. The LOCK bit

is automatically set when the Flash bit WMS of the FCR0H register is

set.

The LOCK bit is the only bit the user can always access to detect the

status of the Flash. If it is low, the remainder of the FCR0L and all other

Flash registers are accessible by the user.

Note: When the LOCK bit is low, the FER register content can be read,

but, its content is updated only when the BSY bits are reset.

Reserved

2-1

BSY[3:2]

Bank 3:2 busy (XFlash)

These bits indicate that a write operation is running on the

corresponding bank of XFlash. They are automatically set when bit

WMS in the FCR0H register is set. Setting the protection operation

automatically sets the BSY2 bit (since the protection registers are in

Block B2). When both busy (XFlash) bits are set, every read access to

the corresponding bank outputs invalid data (software trap 009Bh),

while every write access to the bank is ignored. At the end of a write

operation or during a program or erase suspend these bits are

automatically reset and the bank returns to read mode. After a program

or erase resume these bits are automatically reset.

Reserved

Table 11.

FCR0L register decription (continued)

BIt

Bit name

Function

Obsolete

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