ST10F296 datasheet(87/346 Pages) STMICROELECTRONICS

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ST10F296E

The bootstrap loader

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6.6.4

ST10 configuration in alternate boot mode

When the ST10F296E has entered BSL mode via CAN, the configuration shown in Table 42

is automatically set (values that deviate from the normal reset values, are marked in bold

italic).

Even if the internal IFlash is enabled, no code can be executed out of it.

Warning:

As the XFlash is needed, the XPERCON register is configured

by the ABM loader code and the XPEN bit of the SYSCON

To do this:

●

Copy a function into DPRAM that can do the following:

–

Disable the XPeripherals by clearing the XPEN bit in the SYSCON register

–

Enable the XPeripherals that are needed by writing the correct value in the

XPERCON register

–

Set the XPEN bit in the SYSCON register

–

Return to the calling address

●

Call the function from XFlash

Changing the XPERCON value can not be executed from the XFlash because the XFlash is

disabled when the XPEN bit in the SYSCON register is cleared.

Note:

The settings can be modified if the EINIT instruction is not executed (and is not in the

bootstrap loader code).

Table 42.

ST10 configuration in alternate boot mode

Watchdog timer

Disabled

0404H

(1)

In bootstrap modes (standard or alternate) the ROMEN bit, bit 10 of the SYSCON register, is always set

regardless of the EA pin level. The BYTDIS bit, bit 9 of the SYSCON register, is set according to the data

bus width selection via Port 0 configuration.

XPEN bit set

Context pointer CP

FA00H

Stack pointer SP

FA40H

FC00H

Acc. to startup

config.(2)

BUSCON0 is initialized with 0000h which disables the external bus if pin EA is high during reset. If pin EA

is low during reset, the BUSACT0 bit, bit 10, and the ALECTL0 bit, bit 9, are set, enabling the external bus

with a lengthened ALE signal. BTYP field, bit 7 and 6, is set according to Port 0 configuration.

XPERCON

002DH

XRAM1-2, XFlash, CAN1 enabled

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