ST10F296 datasheet(213/346 Pages) STMICROELECTRONICS

213 / 346 page

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296E

Watchdog timer

213/346

If a bidirectional reset is enabled, and if the RSTIN pin is latched low at the end of an

internal reset sequence, a short hardware reset, a software reset or a watchdog reset

triggers a long hardware reset. Thus, reset indications flags are set to indicate a long

hardware reset.

The watchdog timer is 16-bits in length and is clocked with the system clock divided by 2 or

128. The high byte of the watchdog timer register can be set to a prespecified reload value

(stored in WDTREL).

Each time the high byte of the watchdog timer is serviced by the application software, it is

reloaded. For security reasons, the WDTCON register should be rewritten each time before

the watchdog timer is serviced

Table 129 and Table 130 show the watchdog time range for 40 MHz and 64 MHz CPU clock

respectively.

The watchdog timer period is calculated using the following formula:

Equation 21

Table 129.

WDTREL reload value (fCPU = 40 MHz)

Reload value in WDTREL

Prescaler for fCPU = 40 MHz

2 (WDTIN = 0)

128 (WDTIN = 1)

FFh

12.8 µs

819.2 µs

00h

3.277 ms

209.7 ms

Table 130.

WDTREL reload value (fCPU = 64 MHz)

Reload value in WDTREL

Prescaler for fCPU = 64 MHz

2 (WDTIN = 0)

128 (WDTIN = 1)

FFh

8 µs

512 µs

00h

2.048 ms

131.1 ms

WDT

CPU

⁄

512

WDTIN

[] 63

()

256

WDTREL

[]

–

()

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296 데이터시트(PDF) 213 Page - STMicroelectronics

ST10F296 데이터시트(HTML) 213 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL