ST10F296 datasheet(218/346 Pages) STMICROELECTRONICS

218 / 346 page

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System reset

ST10F296E

218/346

Figure 76.

Asynchronous power-on reset (EA = 0)

Three to eight TCL depending on clock source selection.

20.2.2

Hardware reset

An asynchronous reset is used to recover from catastrophic situations of the application. It

may be triggered by the hardware of the application. Internal hardware logic and application

circuitry are described in Section 20.7: Reset circuitry on page 233 and in Figure 88,

Figure 89 and Figure 91. Asynchronous resets occur when the RSTIN pin is low and the

RPD pin is detected (or becomes) low.

RSTIN

P0[15:13]

P0[12:2]

Not t.

Transparent

Not t.

P0[1:0]

Not t.

Not transparent

V18

XTAL1

...

3..8 TCL(1)

RST

Latching point of Port 0 for

system start-up configuration

VDD

≥ 1 ms (for on-chip VREG stabilization)

RPD

ALE

≥ 1.2 ms (for resonator oscillation + PLL stabilization)

≥ 10.2 ms (for crystal oscillation + PLL stabilization)

RSTF

≤500 ns

(after filter)

≥ 50 ns

8 TCL

Transparent

3..4 TCL

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Product(s)

- Obsolete

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ST10F296 데이터시트(PDF) 218 Page - STMicroelectronics

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