ST10F296 datasheet(335/346 Pages) STMICROELECTRONICS

335 / 346 page

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ST10F296E

Electrical characteristics

335/346

Figure 116. READY and CLKOUT

Cycle as programmed, including MCTC wait states (example shows 0 MCTC wait states).

The leading edge of the respective command depends on R/W delay.

READY sampled high at this sampling point generates a READY controlled wait state, READY sampled

low at this sampling point terminates the current running bus cycle.

READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or

WR).

If the asynchronous READY signal does not fulfill the indicated setup and hold times with respect to

CLKOUT (for example, because CLKOUT is not enabled), it must fulfill t37 to be safely synchronized. This

is guaranteed if READY is removed in response to the command (see Note 4).

Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state

may be inserted here. For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles. For a

demultiplexed bus without MTTC wait state this delay is zero.

The next external bus cycle may start here.

t30

t34

t35

t36

t35

t36

t58

t59

t58

t59

wait state

READY

MUX/tri-state(6)

t32

t33

t29

Running cycle(1)

t31

t37

(3)

(5)

t60 (4)

(6)

(2)

(7)

(3)

CLKOUT

ALE

RD, WR

Synchronous

Asynchronous

READY

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ST10F296 데이터시트(PDF) 335 Page - STMicroelectronics

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