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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F769AI 데이터시트(PDF) 154 Page - STMicroelectronics |
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STM32F769AI 데이터시트(HTML) 154 Page - STMicroelectronics |
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154 / 255 page  Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 154/255 DocID029041 Rev 4 Figure 36. MIPI D-PHY HS/LP clock lane transition timing diagram Figure 37. MIPI D-PHY HS/LP data lane transition timing diagram 5.3.14 MIPI D-PHY PLL characteristics The parameters given in Table 53 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 17. Table 53. DSI-PLL characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock - 4 - 100 MHz fPLL_INFIN PFD input clock - 4 - 25 fPLL_OUT PLL multiplier output clock - 31.25 - 500 fVCO_OUT PLL VCO output - 500 - 1000 tLOCK PLL lock time - - - 200 μs |
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