STR710FZ1 datasheet(63/80 Pages) STMICROELECTRONICS

63 / 80 page

STR71xFxx STR710RZ

Electrical parameters

Doc ID 10350 Rev 13

63/80

4.3.9

BSPI - buffered serial peripheral interface

Subject to general operating conditions for VDD, TA and fPCLK1 ,unless otherwise specified.

Refer to I/O port pin characteristics on page 51 for more details on the input/output alternate

function characteristics (SS, SCK, MOSI, MISO).

Table 36.

BSPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master

fPCLK1/254

fPCLK1/6

5.5

MHz

Slave

fPCLK1/8

3.3

tr(SCK)

tf(SCK)

SPI clock rise and fall time

capacitive charge

C=50 pF

tsu(SS)

(1)

SS setup time

Slave

th(SS)

(1)

SS hold time

Slave

tw(SCKH)

(1)

tw(SCKL)

(1)

SCK high and low time

Master fPCLK1=33 MHz,

presc = 6

tsu(MI)

(1)

tsu(SI)

(1)

Data input setup time

Master

Slave

th(MI)

1)(2)

th(SI)

1)(2)

Data input hold time

Master

Slave

1xtPCLK1

2xtPCLK1

th(MI)

(1)

th(SI)

(1)

Data input hold time

Master fPCLK1=33 MHz

Slave fPCLK1=33 MHz

ta(SO)

1)(3)

Data output access time

Slave

1.5xtPCLK1+42

Slave fPCLK1=33 MHz

tdis(SO)

(1)(4)

Data output disable time

Slave

tv(SO)

(1)(2)

Data output valid time

Slave (after enable edge)

3xtPCLK1+45

fPCLK1=33 MHz

135

th(SO)

(1)

Data output hold time

Slave (after enable edge)

tv(MO)

(1)(2)

Data output valid time

Master (after enable edge)

2xtPCLK1+12

fPCLK1=33 MHz

th(MO)

(1)

Data output hold time

Master (after enable edge)

Data based on design simulation and/or characterisation results, not tested in production.

Depends on fPCLK1. For example, if fPCLK1=8 MHz, then tPCLK1 = 1/fPCLK1 =125 ns and tv(MO) = 255 ns.

Min. time is the minimum time to drive the output and the max. time is the maximum time to validate the data.

Min time is the minimun time to invalidate the output and the max time is the maximum time to put the data in Hi-Z.

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