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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HT45F3W 데이터시트(PDF) 63 Page - Holtek Semiconductor Inc |
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HT45F3W 데이터시트(HTML) 63 Page - Holtek Semiconductor Inc |
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63 / 167 page  Rev. 1.50 �� De�e��e� 01� �01� Rev. 1.50 �3 De�e��e� 01� �01� HT45F3W R-Type Blood Pressure Meter Flash MCU HT45F3W R-Type Blood Pressure Meter Flash MCU Watchdog Timer Operation TheWatchdogTimeroperatesbyprovidingadeviceresetwhenitstimeroverflows.Thismeans thatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallyclearthe WatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisis doneusingtheclearwatchdoginstructions. Undernormalprogramoperation,aWatchdogTimertime-outwillinitialiseadeviceresetandset thestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimer time-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStack Pointerwillbereset.ThreemethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer. ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101Bwrittenintothe WE4~WE0bitfiled,thesecondisusingtheWatchdogTimersoftwareclearinstructionsandthe thirdisviaaHALTinstruction. TherearetwomethodsofusingsoftwareinstructionstocleartheWatchdogTimer,oneofwhich mustbechosenbyconfigurationoption.Thefirstoptionistousethesingle“CLRWDT”instruction whilethesecondistousethetwocommands“CLRWDT1”and“CLRWDT2”.Forthefirstoption, asimpleexecutionofCLRWDTwillcleartheWDTwhileforthesecondoption,both“CLR WDT1”and“CLRWDT2”mustbothbeexecutedalternatelytosuccessfullycleartheWatchdog Timer.Notethatforthissecondoption,if“CLRWDT1”isusedtocleartheWatchdogTimer, successiveexecutionsofthisinstructionwillhavenoeffect,onlytheexecutionofa“CLRWDT2” instructionwillcleartheWatchdogTimer.Similarlyafterthe“CLRWDT2”instructionhasbeen executed,onlyasuccessive“CLRWDT1”instructioncancleartheWatchdogTimer. Themaximumtimeoutperiodiswhenthe218divisionratioisselected.Asanexample,witha 32.768kHzLXToscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround 8secondforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.Ifthe fSYS/4clockisusedastheWatchdogTimerclocksource,itshouldbenotedthatwhenthesystem enterstheSLEEPorIDLE0Mode,thentheinstructionclockisstoppedandtheWatchdogTimer mayloseitsprotectingpurposes.Forsystemsthatoperateinnoisyenvironments,usingthefSUB clocksourceisstronglyrecommended. WE4~WE0 �its WDTC Registe� Reset MCU fS CLR “HALT” Inst�u�tion fSUB M U X Configu�ation option M U X fSYS/4 LXT LIRC Configu�ation option 8-stage Divide� WDT P�es�ale� fS/�8 8-to-1 MUX WS�~WS0 WDT Ti�e-out “CLR WDT1 and CLR WDT�” o� “CLR WDT” Inst�u�tion Configu�ation option Watchdog Timer |
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