HT82M9BA datasheet(9/44 Pages) HOLTEK

9 / 44 page

HT82M9BE/HT82M9BA

Rev. 1.80

December 22, 2008

a branch to a subroutine at a specified location in the

program memory. Only the program counter is pushed

onto the stack. If the contents of the register or status

program which corrupts the desired control sequence,

the contents should be saved in advance.

The USB interrupts are triggered by the following USB

events and the related interrupt request flag (USBF; bit

4 of the INTC) will be set.

· Access of the corresponding USB FIFO from PC

· The USB suspend signal from PC

· The USB resume signal from PC

· USB Reset signal

When the interrupt is enabled, the stack is not full and

the external interrupt is active, a subroutine call to loca-

tion 04H will occur. The interrupt request flag (USBF)

and EMI bits will be cleared to disable other interrupts.

When the PC Host access the FIFO of the HT82M9BE/

HT82M9BA, the corresponding request bit of the USR is

set, and a USB interrupt is triggered. So user can easily

decide which FIFO is accessed. When the interrupt has

been served, the corresponding bit should be cleared by

firmware. When the HT82M9BE/HT82M9BA receives a

USB Suspend signal from the Host PC, the suspend line

(bit0 of the USC) of the HT82M9BE/HT82M9BA is set

and a USB interrupt is also triggered.

When the HT82M9BE/HT82M9BA receives a Resume

signal from the Host PC, the resume line (bit3 of the

USC) of the HT82M9BE/HT82M9BA are set and a USB

interrupt is triggered.

Whenever a USB reset signal is detected, the USB in-

terrupt is triggered and URST_Flag bit of the USC regis-

ter is set. When the interrupt has been served, the bit

should be cleared by firmware.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (bit 5 of the INTC), caused by a Timer 0

overflow. When the interrupt is enabled, the stack is not

full and the T0F bit is set, a subroutine call to location

08H will occur. The related interrupt request flag (T0F)

will be reset and the EMI bit cleared to disable further in-

terrupts.

Bit No.

Label

Function

EMI

Controls the master (global) interrupt (1=enable; 0=disable)

EUI

Controls the USB interrupt (1=enable; 0= disable)

ET0I

Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)

ET1I

Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)

USBF

USB interrupt request flag (1=active; 0=inactive)

T0F

Internal Timer/Event Counter 0 request flag (1:active; 0:inactive)

T1F

Internal Timer/Event Counter 1 request flag (1:active; 0:inactive)

Unused bit, read as

²0²

INTC (0BH) Register

Bit No.

Label

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

1AC

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

3OV

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

4PDF

PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by

executing the

²HALT² instruction.

5TO

TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

6~7

Unused bit, read as

²0²

Status (0AH) Register

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