HT82M9BE/HT82M9BA

Rev. 1.80

19

December 22, 2008

The MISC register is actually a command + status to control the desired FIFO action and to show the status of the de-

sired FIFO. Every bit

¢s meaning and usage are listed as follows:

Bit No.

Function

Read/Write

Register Address

7

Len0

R/W

01000110B

6

Ready

R

5

Set CMD

R/W

4

Sel_pipe1

R/W

3

Sel_pipe0

R/W

2

Clear

R/W

1Tx

R/W

0

Request

R/W

MISC (46H) Registers Table

Function

Name

Read/Write

Description

Request

R/W

After setting the other desired status, FIFO can be requested by setting this bit high ac-

tive. After work has been done, this bit must be set low.

Tx

R/W

Represents the direction and transition end of the MCU accesses. When being set as

logic 1, the MCU wants to write data to FIFO. After work has been done, this bit must be

set to logic 0 before terminating the request to represent a transition end. For reading

action, this bit must be set to logic 0 to indicate that the MCU wants to read and must be

set to logic 1 after work is done.

Clear

R/W

Represents MCU clear requested FIFO, even if FIFO is not ready.

Sel_pipe1

Sel_pipe0

R/W

Determines which FIFO is desired,

²00² for FIFO0, ²01² for FIFO1, ²10² for FIFO 2 and

²11² for FIFO3

Set CMD

R/W

Shows that the data in FIFO is setup as command. This bit will be cleared by firmware.

So, even if the MCU is busy, nothing is missed by the SETUP command from the host.

Ready

R

Indicates that the desired FIFO is ready to work.

Len0

R/W

Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a

read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after

the next valid SETUP token is received.

MISC Function Table

The HT82M9BE/HT82M9BA have two 8

´8 bidirectional

FIFO for the three endpoints (control and Interrupt).

User can easily read/write the FIFO data by accessing

the corresponding FIFO pointer register (FIFO0, FIFO1,

FIFO2, FIFO3). The following are two examples for

reading and writing the FIFO data:

HT82M9BE/HT82M9BA FIFO is read by packet. To read

from FIFO, the following should be followed:

TX bit = 0), and set the REQ bit to

²1².

the data number that has been read.

which indicates the end of the FIFO data reading.

User reads the data through the FIFO pointer register,

user has to record the number of bytes to be read.

The HT82M9BE/HT82M9BA allows a maximum of 8

bytes of data in each packet.

The HT82M9BE/HT82M9BA FIFO is written by packet.

To write to FIFO, the following should be followed:

bit = 1), and set the REQ bit to

²1²

the data number that has been written

ready bit becomes 0 which indicates that the FIFO no

longer allows any data writing.

User writes the data through the FIFO pointer register,

user has to record the number of bytes that have been

written. The HT82M9BE/HT82M9BA allows a maximum

of 8 bytes of data in each packet.