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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IRCC 데이터시트(PDF) 24 Page - SMSC Corporation |
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IRCC 데이터시트(HTML) 24 Page - SMSC Corporation |
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24 / 79 page  24 REGISTERS The IrCC is partially enabled through binary controls found in two 8-byte register banks. The banks, the ACE550 UART Controls and the SCE Controls, are selected with the nACE and nSCE register-bank selector inputs found in the Interface Description. If nACE is zero, the three least significant bits of the Host Address Bus decode the 16550A UART control registers. If nSCE is zero, the SCE control bank is addressed. All of the IrCC registers are 8 bits wide. ACE UART CONTROLS The table below (Table 12) lists the ACE UART Control Registers (see the ACE UART section). Table 12 - 16550A UART Addressing DLAB A2 A1 A0 DIRECTION REGISTER NAME 0 0 0 0 Read Receive Buffer 0 0 0 0 Write Transmit Buffer 0 0 0 1 Read/Write Interrupt Enable X 0 1 0 Read Interrupt Identification X 0 1 0 Write FIFO Control X 0 1 1 Read/Write Line Control X 1 0 0 Read/Write Modem Control X 1 0 1 Read/Write Line Status X 1 1 0 Read/Write Modem Status X 1 1 1 Read/Write Scratchpad 1 0 0 0 Read/Write Divisor (LSB) 1 0 0 1 Read/Write Divisor (MSB) |
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