IRCC datasheet(29/79 Pages) SMSC

29 / 79 page

CRC Error, bit 3

The CRC Error bit is set to one following Frame-

Check-Sequence errors in IrDA FIR receive

message frames.

Frame Abort, bit 2

The Frame Abort bit is set to one following; 1) a

forced abort, i.e. after setting the Abort bit to one

in Line Control Register A; 2) an IrDA FIR FIFO

underrun with the Data Done bit inactive during

transmit; 3) an IrDA FIR FIFO Overrun during

receive; 4) framing errors in IrDA FIR payload

data during receive. NOTE: The Frame Abort bit

will not go active during transmit if the Tx Data

Size register decrements to zero when the last

byte is read from the FIFO with the Data Done bit

not set.

Status Register Address, bits 0 - 2 (write-

only)

Three Status Register Address bits control

software access to, and reside at the same

address as, the Line Status Registers.

The

Status Register Address bits are write-only and

occupy bits D0 to D2. To access any one of the

eight Line Status Registers, first write the

address of the appropriate register (0 - 7), then

read the register's contents.

Line Control Register A (Address 4)

FIFO Reset, bit 7

When set to one, the FIFO Reset bit clears the

FIFO Full and Not Empty flags in the 128-byte

SCE FIFO. The FIFO Reset bit is automatically

set to zero following the re-initialization.

Fast, bit 6

The Fast bit controls the state of an uncommitted

IrCC output, Fast. The bit is read/write.

General Purpose Data, bit 5

The General Purpose Data bit controls the state

of an uncommitted IrCC output, GP Data. The

bit is read/write.

Raw Tx, bit 4

The Raw Tx bit controls the state of the infrared

emitter in Raw IR mode. The bit is read/write.

Raw Rx, bit 3

The Raw Rx bit represents the state of the

infrared detector in Raw IR mode. The bit is

read-only.

Abort, bit 2

The Abort bit is used to terminate transmit

messages in progress; i.e., once the transmitter

has been enabled and the line is active. When

the Abort bit is one, the current transmit

message is terminated, the EOM flag is activated

and the SCE FIFO is cleared. The Abort bit is

reset to zero by the End-Of-Frame.

Abort is

used for IrDA FIR transmit mode, only.

Data Done, bit 1

When set to one, the Data Done bit is used

during transmit to distinguish an end-of-valid-

message-data condition from a FIFO Underrun

that

indicates

incomplete

message

data.

Terminal Count automatically activates the Data

Done bit during DMA operations. Note: the Data

Done bit is not activated by TC during receive

operations. Data Done is automatically reset to

zero following the end of a message only if the

FIFO is empty.

Line Control Register B (Address 5)

SCE Modes, bits 6 - 7

The SCE Modes bits enable the SCE transmitter

and receiver (Table 16). These bits are R/W and

must be manually reset by the host following

IrDA message transactions. The SCE Modes

bits are automatically reset by the hardware

following Consumer IR messages. NOTE: the

SCE Modes bits must be zero for loopback tests.

IRCC 데이터시트(PDF) 29 Page - SMSC Corporation

IRCC 데이터시트(HTML) 29 Page - SMSC Corporation

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