IRCC datasheet(31/79 Pages) SMSC

31 / 79 page

Table 17 - Message Flow Control

BRICK

WALL

ENABLE

DATA

DONE

BIT

FIFO

EMPTY

STATE

AFTER

EOF

DESCRIPTION

BOF

Brick Wall Next Message

Idle

Multi-Frame Window Complete, Reset Data Done bit

BOF

Brick Wall Next Message

BOF

Brick Wall Next Message (possible underrun)

Idle

Re-enable Transmitter for Next Message

Idle

Single Message Complete, Reset Data Done bit

Idle

Single Message Complete, Datasize Counter = 0

Idle

Single Message Complete, Datasize Counter = 0

Message Count, bits 0 - 3

The four Message Count bits control hardware

access to the Line Status Registers and are

unaffected by the Status Register Address bits.

The Message Count bits also indicate the system

message-state.

For example, if the Message

Count bits are zero, i.e. the power-up default,

Line Status Register zero is active, although

undefined because no messages have been sent

or received.

The Message Count bits are

incremented after every active frame. At point A

in Figure 18, for example, the rising edge of

nActive Frame increments Message Count by

one indicating that the first message has been

received; i.e., Line Status Register #1 (status

currently

active,

although

undefined.

Hardware prevents the Message

Count

from

exceeding

eight

('1000'Binary). NOTE: IrDA messages beyond

eight frames are ignored.

nActive Frame

Message Count (0000)

0001

0010

0011

FIGURE 18 - MESSAGE COUNT EXAMPLE

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