IRCC datasheet(55/79 Pages) SMSC

55 / 79 page

SCE

DESCRIPTION

The SCE is a half-duplex synchronous serial

communications controller that controls data flow

between the Bus Interface I/O block and the IrDA

FIR

and

Consumer

(TV

Remote)

Encoders (Figure 20). The SCE also includes

partial full-duplex loopback functionality for

diagnostic testing.

Bit rates from .4Kbps to

4Mbps are supported. All of the SCE register

controls are located in the nSCE-addressable 8-

bit Register Blocks.

FRAMING

The SCE operates with and without framing.

With framing implies that the SCE works with the

IrDA FIR encoder/decoder so the required

symbols for the non-payload data portions of the

.576Mbps, 1.152Mbps and 4Mbps packets can

be generated.

Without framing implies that the

SCE acts simply as serial-to-parallel converter

for the Consumer IR (TV Remote) encoder/

decoder.

ACTIVE FRAME INDICATOR

The SCE signal nActiveFrame is a PLA state

variable that is synchronized to both IrDA FIR

and

Consumer

message

frames.

nActiveFrame cycles high and low for each

message frame, regardless of the state of the

Brick Wall bit. nActiveFrame is primarily used to

trigger active frame interrupts and to advance the

Message Count bits that control hardware

access to the Line Status Registers.

IrDA Modes

Transmit

nActiveFrame goes active as soon as the IrDA

transmitter

initiates

BOF

sequence.

nActiveFrame becomes inactive as soon as the

IrDA transmitter completes an EOF sequence.

In the case of a transmit abort, nActiveFrame

becomes inactive as soon as the IrDA transmitter

completes the abort sequence.

Receive

nActiveFrame goes active as soon as the IrDA

receiver detects valid payload data; i.e., after a

valid BOF sequence.

nActiveFrame becomes

inactive as soon as the IrDA receiver detects an

EOF sequence. In the case of a FIFO Overrun

or abort, nActiveFrame becomes inactive as

soon as the IrDA receiver updates the status

Serial-to-Parallel

Converter

Parallel-to-Serial

Converter

16/32-bit

CRC Generator

16/32-bit

CRC Checker

Timing

Control

Transmit

Receive

Controls

FIR/TV

Encoder

FIR/TV

Decoder

FIGURE 20 - SCE BLOCK DIAGRAM

IRCC 데이터시트(PDF) 55 Page - SMSC Corporation

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