WM8972LEFLSLASHR datasheet(29/49 Pages) WOLFSON

29 / 49 page

Preliminary Technical Data

WM8972L

PTD Rev 2.2 June 2004

MASTER AND SLAVE MODE OPERATION

The WM8972L can be configured as either a master or slave mode device. As a master device the

WM8972L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data

transfer on ADCDAT and DACDAT. In slave mode, the WM8972L responds with data to clocks it

receives over the digital audio interface. The mode can be selected by writing to the MS bit (see

Table 23). Master and slave modes are illustrated below.

Figure 11 Master Mode

Figure 12 Slave Mode

AUDIO DATA FORMATS

The mono data is available during the left channel period of DACLRC/ADCLRC.

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

Figure 13 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.

Figure 14 Right Justified Audio Interface (assuming n-bit word length)

BCLK

ADCDAT

ADCLRC

DACDAT

DACLRC

WM8972

CODEC

DSP

ENCODER/

DECODER

Note: The ADC and DAC can run at different sample rates

BCLK

ADCDAT

ADCLRC

DACDAT

DACLRC

WM8972

CODEC

DSP

ENCODER/

DECODER

Note: The ADC and DAC can run at different sample rates

WM8972LEFL/R 데이터시트(PDF) 29 Page - Wolfson Microelectronics plc

WM8972LEFL/R 데이터시트(HTML) 29 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

데이터시트 다운로드

링크 URL