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WM8972LEFL/R 데이터시트(PDF) 30 Page - Wolfson Microelectronics plc |
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WM8972LEFL/R 데이터시트(HTML) 30 Page - Wolfson Microelectronics plc |
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30 / 49 page ![]() WM8972L Preliminary Technical Data w PTD Rev 2.2 June 2004 30 In I 2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. Figure 15 I 2S Justified Audio Interface (assuming n-bit word length) In DSP mode, the mono MSB is available on either the 1 st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRCLK. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB and the next sample. Figure 16 DSP Mode Audio Interface (mode A, LRP=0) Figure 17 DSP Mode Audio Interface (mode B, LRP=1) |
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