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WM8972LEFL/R 데이터시트(PDF) 31 Page - Wolfson Microelectronics plc

부품명 WM8972LEFL/R
상세설명  MONO CODEC FOR PORTABLE AUDIO APPLICATIONS
PDF  49 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
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WM8972LEFL/R 데이터시트(HTML) 31 Page - Wolfson Microelectronics plc

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Preliminary Technical Data
WM8972L
w
PTD Rev 2.2 June 2004
31
AUDIO INTERFACE CONTROL
The register bits controlling audio format, word length and master / slave mode are summarised in
Table 24. MS selects audio interface operation in master or slave mode. In Master mode BCLK,
ADCLRC and DACLRC are outputs. The frequency of ADCLRC and DACLRC is set by the sample
rate control bits SR[4:0] and USB. In Slave mode BCLK, ADCLRC and DACLRC are inputs.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
7
BCLKINV
0
BCLK invert bit (for master & slave
modes)
0 = BCLK not inverted
1 = BCLK inverted
6
MS
0
Master / Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
right, left & i2s modes – LRCLK polarity
1 = invert LRCLK polarity
0 = normal LRCLK polarity
4
LRP
0
DSP Mode – mode A/B select
1 = MSB is available on 1st BCLK rising
edge after LRC rising edge (mode B)
0 = MSB is available on 2nd BCLK rising
edge after LRC rising edge (mode A)
3:2
WL[1:0]
10
Audio Data Word Length
11 = 32 bits (see Note)
10 = 24 bits
01 = 20 bits
00 = 16 bits
R7 (07h)
Digital Audio
Interface
Format
1:0
FORMAT[1:0]
10
Audio Data Format Select
11 = DSP Mode
10 = I
2S Format
01 = Left justified
00 = Right justified
Table 24 Audio Data Format Control
Note: Right Justified mode does not support 32-bit data.
AUDIO INTERFACE OUTPUT TRISTATE
Register bit TRI, register 24(18h) bit[3] can be used to tristate the ADCDAT pin and switch ADCLRC,
DACLRC and BCLK to inputs. In Slave mode (MASTER=0) ADCLRC, DACLRC and BCLK are by
default configured as inputs and only ADCDAT will be tri-stated, (see Table 25).
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R24(18h)
Additional
Control (2)
3
TRI
0
Tristates ADCDAT and switches ADCLRC,
DACLRC and BCLK to inputs.
0 = ADCDAT is an output, ADCLRC, DACLRC
and BCLK are inputs (slave mode) or outputs
(master mode)
1 = ADCDATE is tristated, ADCLRC, DACLRC
and BCLK are inputs
Table 25 Tri-stating the Audio Interface



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