PIC12CE673-04SLASHP datasheet(28/116 Pages) MICROCHIP

28 / 116 page

PIC12CE67X

DS40181B-page 28

Preliminary

FIGURE 6-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 6-2:

ACKNOWLEDGE TIMING

(A)

(B)

(C)

(D)

(A)

(C)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this point

so the Transmitter can continue sending data.

Data from transmitter

SDA

Acknowledge

Bit

6.2

Device Addressing

After generating a START condition, the processor

transmits a control byte consisting of a EEPROM

address and a Read/Write bit that indicates what type

of operation is to be performed. The EEPROM address

consists of a 4-bit device code (1010) followed by three

don't care bits.

The last bit of the control byte determines the operation

to be performed. When set to a one a read operation is

selected, and when set to a zero a write operation is

selected. (Figure 6-3). The bus is monitored for its cor-

responding EEPROM address all the time. It generates

an acknowledge bit if the EEPROM address was true

and it is not in a programming mode.

FIGURE 6-3:

CONTROL BYTE FORMAT

ACK

R/W

Device Select

Bits

Don’t Care

Bits

EEPROM Address

Acknowledge Bit

Start Bit

Read/Write Bit

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