LED171596ARSLR datasheet(23/153 Pages) TI1

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VLED

VDDIO

VDD

STATE

RESET

STANDBY

NORMAL

EN pin

EN_BACKLIGHT[0]

HS0-3

LED0-23

SHUTDOWN

LED171596A

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SNVSAY2 – OCTOBER 2017

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Device Functional Modes (continued)

Figure 19. Shut-Down Sequence Diagram

7.5 Programming

7.5.1 Serial Interfaces

The LED171596A supports two serial interfaces: I2C and 16-bit SPI. Sampling of IFSEL_LATCH pin happens

after the rising edge of EN pin. After detection of the selected interface, the IFSEL_LATCH pin can be used to

latch written SRAM data to internal processing. The minimum pulse width for LATCH signal is 500 ns. Interface

selection for the IFSEL_LATCH pin is:

•

0 – SPI mode

•

1 – I2C-compatible mode

7.5.1.1 SPI Interface

In SPI mode host can address as many unique LED171596A devices as there are slave select pins on host. The

complete register space in LED171596A can be accessed using SPI interface. Rising edge of IFSEL_LATCH pin

or LATCH bit are used to latch written SRAM data to internal processing.

The LED171596A is compatible with SPI serial-bus specification and operates as a slave device. The

transmission consists of 32-bit write and read cycles. One cycle consists of 15-bit address (9 bits used), 1

read/write (R/W) bit and 16-bit data (9 bits used) to maintain compatibility with16-bit SPI.

The R/W bit high state defines a write cycle and low defines a read cycle. The MISO output is normally in a high-

impedance state. When the slave-select pin SS for the device is active (that is, low) the MISO output is pulled

low for read only. During write cycle MISO stays in high-impedance state. This allows the host to write data to

multiple LED171596A slave devices simultaneously if the SS pin is pulled low on all devices. The address and

data bits are transmitted MSB first. The slave-select signal SS must be low during the cycle transmission. SS

resets the interface when high, and it has to be taken high between successive cycles, except when using auto-

increment mode. Data is clocked in on the rising edge of the SCK clock signal, while data is clocked out on the

falling edge of SCK.

LED171596ARSLR 데이터시트(PDF) 23 Page - Texas Instruments

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