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LED171596ARSLR 데이터시트(PDF) 8 Page - Texas Instruments |
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LED171596ARSLR 데이터시트(HTML) 8 Page - Texas Instruments |
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8 / 153 page ![]() 8 LED171596A SNVSAY2 – OCTOBER 2017 www.ti.com Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Limits apply over the full ambient temperature range –40°C < TA < +85°C. Unless otherwise specified: VDD = 3.3 V, VDDIO = 3.3 VLED = 5 V, ILED_PK = 60 mA, CVLED = 10 µF, CVDD = 1 µF. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VSDOOH Output high level IOUT = –2 mA 0.7 × VDDIO 0.9 × VDDIO V ISDOLEAK Output leakage current VPIN ≤ VDDIO 1 µA LOGIC OUTPUT SDA VSDAOL Output low level IOUT = 3 mA 0.3 0.5 V ISDALEAKAGE Output leakage current VSDA = VDDIO = 3.5 V 1 µA 6.6 Timing Requirements for EN, IFSEL_LATCH MIN TYP MAX UNIT tEN Time from EN rising edge until SPI or I2C first access 5 ms tDISABLE EN low time for reset detection 0.125 ms tIFSEL_HOLD IFSEL_LATCH hold time following EN rising edge 1 ms tLATCH Minimum LATCH pulse width 500 ns 6.7 Timing Requirements for SPI Interface MIN TYP MAX UNIT t1 Cycle time 100 ns t2 Enable lead time 50 ns t3 Enable lag time 50 ns t4 Clock low time 45 ns t5 Clock high time 45 ns t6 Data setup time 20 ns t7 Data hold time 20 ns t8 Disable time 30 ns t9 Data valid 35 ns t10 SS inactive time 50 ns Cb Bus capacitance 5 40 pF |
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