ADAV801ASTZ datasheet(39/61 Pages) AD

39 / 61 page

ADAV801

Rev. A | Page 38 of 60

Transmitter Message Zeros Most Significant Byte—Address 0001111 (0x0F)

Table 43. Transmitter Message Zeros Most Significant Byte Register Bit Map

MSBZeros7

MSBZeros6

MSBZeros5

MSBZeros4

MSBZeros3

MSBZeros2

MSBZeros1

MSBZeros0

Table 44. Transmitter Message Zeros Most Significant Byte Register Bit Description

Bit Name

Description

MSBZeros[7:0]

Most significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets).

Default = 0x00.

Transmitter Message Zeros Least Significant Byte—Address 0010000 (0x10)

Table 45. Transmitter Message Zeros Least Significant Byte Register Bit Map

LSBZeros7

LSBZeros6

LSBZeros5

LSBZeros4

LSBZeros3

LSBZeros2

LSBZeros1

LSBZeros0

Table 46. Transmitter Message Zeros Least Significant Byte Register Bit Descriptions

Bit Name

Description

LSBZeros[7:0]

Least significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x09.

Autobuffer—Address 0010001 (0x11)

Table 47. Autobuffer Register Bit Map

Reserved

Zero_Stuff_IU

Auto_UBits

Auto_CSBits

IU_Zeros3

IU_Zeros2

IU_Zeros1

IU_Zeros0

Table 48. Autobuffer Register Bit Descriptions

Bit Name

Description

Zero_Stuff_IU

Enables the addition or subtraction of zeros between IUs during autobuffering of the user bits in IEC60958-3 format.

0 = No zeros added or subtracted.

1 = Zeros can be added or subtracted between IUs.

Auto_UBits

Enables the user bits to be autobuffered between the AES3/S/PDIF receiver and transmitter.

0 = User bits are not autobuffered.

1 = User bits are autobuffered.

Auto_CSBits

Enables the channel status bits to be autobuffered between the AES3/S/PDIF receiver and transmitter.

0 = Channel status bits are not autobuffered.

1 = Channel status bits are autobuffered.

IU_Zeros[3:0]

Sets the maximum number of zero-stuffing to be added between IUs while autobuffering up to a maximum of 8.

0000 = 0.

0001 = 1.

…

0111 = 7.

1000 = 8.

Sample Rate Ratio MSB—Address 0010010 (0x12)

Table 49. Sample Rate Ratio MSB Register (Read-Only) Bit Map

Reserved

SRCRATIO14

SRCRATIO13

SRCRATIO12

SRCRATIO11

SRCRATIO10

SRCRATIO09

SRCRATIO08

Table 50. Sample Rate Ratio MSB Register (Read-Only) Bit Descriptions

Bit Name

Description

SRCRATIO[14:8]

Seven most significant bits of the15-bit sample rate ratio.

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