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ADAV801ASTZ 데이터시트(PDF) 53 Page - Analog Devices

부품명 ADAV801ASTZ
상세설명  Audio Codec for Recordable DVD
PDF  61 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
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ADAV801ASTZ 데이터시트(HTML) 53 Page - Analog Devices

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ADAV801
Rev. A | Page 52 of 60
PLL Control Register 1—Address 1110100 (0x74)
Table 128. PLL Control Register 1 Bit Map
7
6
5
4
3
2
1
0
DIRIN_CLK1
DIRIN_CLK0
MCLKODIV
PLLDIV
PLL2PD
PLL1PD
XTLPD
SYSCLK3
Table 129. PLL Control Register 1 Bit Descriptions
Bit Name
Description
DIRIN_CLK[1:0]
Recovered S/PDIF clock sent to SYSCLK3.
00 = SYSCLK3 comes from PLL block.
01 = Reserved.
10 = Reserved.
11 = SYSCLK3 is the recovered S/PDIF clock from DIRIN.
MCLKODIV
Divide input MCLK by 2 to generate MCLKO.
0 = Disabled.
1 = Enabled.
PLLDIV
Divide XIN by 2 to generate the PLL master clock.
0 = Disabled.
1 = Enabled.
PLL2PD
Power-down PLL2.
0 = Normal.
1 = Power-down.
PLL1PD
Power-down PLL1.
0 = Normal.
1 = Power-down.
XTLPD
Power-down XTAL oscillator.
0 = Normal.
1 = Power-down.
SYSCLK3
Clock output for SYSCLK3.
0 = 512 × fS.
1 = 256 × fS.



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