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MFC2000 데이터시트(PDF) 286 Page - List of Unclassifed Manufacturers |
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MFC2000 데이터시트(HTML) 286 Page - List of Unclassifed Manufacturers |
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286 / 426 page ![]() MFC2000 Multifunctional Peripheral Controller 2000 Hardware Description 15-6 Conexant 100723A Bit 6-2: RxFIFOQty (Receive FIFO Quantity) Read Only bits. These five bits hold the value of the amount of bytes stored within the receive FIFO. As data is written to or removed from the RxFIFO, the quantity will be adjusted accordingly. Bit 1-0: RxFIFOThreshVal (Receive FIFO Threshhold value) Read/Write bits. Depending on how these two bits are set, will affect when the receive FIFO considers itself full enough to cause an interrupt. Bit Value # of bytes filled in RxFIFO which should cause interrupt “00” 4 “01” 8 “10” 12 “11” 14 Address: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default: SASIrqSts 01FF80F9 (Not Used) (Not Used) (Not Used) RxFifo Overrun (Read only) TxFifoFull (Read only) TxFifoEmpty (Read only) RxFifoFull (Read only) RxFifoEmpt y (Read only) Rst. Value XXh Read Value 05h Address: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default: SASIrqSts 01FF80F8 RxTimeout Elapsed (Read only) RxTimeout Enb TxBufEmpty Or TxFifoThres h (Read only) TxShfEmpty (Read only) RxBufFull Or RxFifoThres h (Read only) TxBufIrqEnb TxShfIrqEnb RxBufIrqEn b Rst. Value X0XXX000b Read Value 30h Register Description: SerSASIrqCtrl Register Bit 15-13: Not Used Bit 12: RxFifoOverrun(Receive FIFO data loss) Read only bit. This bit goes high when the receive FIFO is completely full, but an extra byte has just been received by the RxShiftReg. This will not cause an interrupt, but the RxFifoThresh should already have done so. Bit 11: TxFifoFull(Transmit FIFO full) Read only bit. This bit goes high when the transmit FIFO is completely full. Data cannot be written to the transmit FIFO after this point. This will not cause an interrupt. This is helpful when trying to figure out if more bytes can be written to the transmit FIFO. Bit 10: TxFifoEmpty(Transmit FIFO empty) Read only bit. This bit goes high when the transmit FIFO is completely empty. This will not cause an interrupt, but the TxFifoThresh should have already done so. |
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