MFC2000 datasheet(356/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

19-6

Conexant

100723A

SSCLKPol2

SSCLKPhas2

Description (used for both master and slave modes)

Enable the external logic to clock the SSTXD2 pin on the rising edge of the SSCLK2 pin. The SSCLK2

pin’s first transition will be in the middle of the first bit.

Enable the external logic to clock the SSTXD2 pin on the falling edge of the SSCLK2 pin. The

SSCLK2 pin’s first transition will occur at the beginning of the first bit.

Enable the external logic to clock the SSTXD2 pin on the falling edge of the SSCLK2 pin. The

SSCLK2 pin’s first transition will be in the middle of the first bit.

Enable the external logic to clock the SSTXD2 pin on the rising edge of the SSCLK2 pin. The SSCLK2

pin’s first transition will occur at the beginning of the first bit.

MSB

LSB

SSCLK2

(SSCLKPol2=0,

SSCLKPhas2=0)

SSCLK2

(SSCLKPol2=0,

SSCLKPhas2=1)

SSCLK2

(SSCLKPol2=1,

SSCLKPhas2=0)

SSCLK2

(SSCLKPol2=1,

SSCLKPhas2=1)

SSTXD2

Internal strobe for

data capture(all modes)

Figure 19-3. SSCLK2 Diagram

Note: SSCLK2 is used to synchronize the movement of data both in and out of device through

SSRXD2 and SSTXD2 pins. The master and slave devices are capable of exchanging a data

byte of information during a sequence of eight clock pulses. Both master and slave devices must

be operated in the same timing mode as controlled by SSCLKPol2 and SSCLKPhas2 signals.

Bit 0:

Mode12, Read/Write bit.

This bit controls the SSIF2 master/slave modes.

0: Master (default)

1: Slave

When in the Master Mode, the SSCLK2 pin is configured as an output

pin. When in the Slave Mode, SSCLK2 signal is an input to the SSIF2.

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