MFC2000 datasheet(354/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

19-4

Conexant

100723A

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

SSDiv1

01FF8105

(Not Used)

Rst. Value

xxh

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

SSDiv1

01FF8104

SSInFull1

(Not Used)

SSCLK1 Divisor

Rst. Value

0xxx0000b

Read Value

00h

Bit 7:

SSInFull1, Read bit.

This bit indicates the status of the input register.

0: Empty (default)

1: Full

This bit allows the Firmware to poll the status of the serial interface

when the use of the interrupt is not desired and is cleared by reading

the in SSIF1 Data Register. SSInFull1 is active on the falling edge of

AUXCLK1 and is used by Interrupt controller where it masked.

Bit 6-4:

Not used

Bit 3-0:

DivReg (Divisor Register), Read/Write bits.

The Div Register is the SSCLK1 Divisor Register, which defines the

SSCLK1 frequency. Writing the DivReg register will cause the SSIF1

logic to load the internal counter. Firmware can transmit data with the

right speed immediately after the SSCLK1 setup.

The SSCLK1 Divisor Register defines the SSCLK1 frequency, which depends on the AUXCLK frequency. The

SSCLK1 Divisor Register is a five bit register. The SSCLK1 frequency (fSCK)and Divisor relationship is:

AUXCLK

Divisor

SCK =

)

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