WM8976 datasheet(59/83 Pages) WOLFSON

59 / 83 page

Preliminary Technical Data

WM8976

PTD Rev 2.0 February 2005

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

ADCLRSWAP

Controls whether ADC data appears in

‘right’ or ‘left’ phases of LRC clock:

0=ADC data appear in ‘left’ phase of

LRC

1=ADC data appears in ‘right’ phase of

LRC

DACLRSWAP

Controls whether DAC data appears in

‘right’ or ‘left’ phases of LRC clock:

0=left DAC data appears in left phase of

LRC and vice versa

1=left DAC data appears in right phase

of LRC and vice versa

4:3

FMT

Audio interface Data Format Select:

00=Right Justified

01=Left Justified

10=I

2S format

11= DSP/PCM mode

6:5

Word length

00=16 bits

01=20 bits

10=24 bits

11=32 bits (see note)

LRCP

LRC clock polarity

0=normal

1=inverted

Audio

Interface

Control

BCP

BCLK polarity

0=normal

1=inverted

Table 47 Audio Interface Control

Note: Right Justified Mode will only operate with a maximum of 24 bits.

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below. Each audio interface can be controlled individually.

and LRC are outputs. The frequency of BCLK and LRC in master mode are controlled with

BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses

at the end of a LRC if there is a non-integer ratio of BCLKs to LRC clocks.

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