ATSAMB11XR datasheet(24/87 Pages) MICROCHIP

24 / 87 page

CPU and Memory Subsystem

7.1

ARM Subsystem

The ATSAMB11-XR2100A and ATSAMB11-ZR210CA have an ARM Cortex-M0 32-bit processor. It is

responsible for controlling the BLE Subsystem and handling all application features.

The Cortex-M0 Microcontroller consists of a full 32-bit processor capable of addressing 4GB of memory. It

has a RISC like load/store instruction set and internal 3-stage Pipeline Von Neumann architecture.

The Cortex-M0 processor provides a single system-level interface using AMBA technology to provide

high speed, low latency memory accesses.

The Cortex-M0 processor implements a complete hardware debug solution with four hardware breakpoint

and two watchpoint options. This provides high system visibility of the processor, memory, and

peripherals through a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other

small package devices.

ATSAMB11 is running a proprietary RTOS tightly coupled with FW in the ROM and the user can not

override it. SysTick timer is being used by the stack and will not be available for usage by the application.

Figure 7-1. ARM Cortex-M0 Subsystem

ATSAMB11XR/ZR

Datasheet Preliminary

DS70005342A-page 24

ATSAMB11XR 데이터시트(PDF) 24 Page - Microchip Technology