ATSAMB11XR datasheet(41/87 Pages) MICROCHIP

41 / 87 page

9.6

Analog to Digital Converter (ADC)

9.6.1

Overview

The ATSAMB11-XR2100A and ATSAMB11-ZR210CA have an integrated Successive Approximation

blocks are the capacitive DAC, comparator, and synchronous SAR engine as illustrated in Figure 9-3.

Figure 9-3. SAR ADC Block Diagram

The ADC reference voltage can be either generated internally or set externally via one of the four

available Mixed Signal GPIO pins on the ATSAMB11-XR2100A and the ATSAMB11-ZR210CA.

There are two modes of operation:

•

High resolution (11-bit): Set the reference voltage to half the supply voltage or below. In this

condition the input signal dynamic range is equal to twice the reference voltage (ENOB=10-bit).

•

Medium Resolution (10-bit) : Set the reference voltage to any value below supply voltage (up to

supply voltage - 300 mV) and in this condition the input dynamic range is from zero to the reference

voltage (ENOB = 9-bit).

Four input channels are time multiplexed to the input of the SAR ADC. However, on the ATSAMB11, only

four channel inputs are accessible from the outside, through the Mixed Signal GPIO pin numbers listed in

Table 9-1.

In power saving mode, the internal reference voltage is completely off and the reference voltage is set

externally.

The ADC characteristics are summarized in Table 9-5.

Table 9-5. SAR ADC Characteristics

Conversion rate

1 ks → 1 MS

Selectable Resolution

10 → 11 bit

Power consumption

13.5 µA (at 100 KS/s) (1)

Note:

With external reference.

ATSAMB11XR/ZR

Datasheet Preliminary

DS70005342A-page 41

ATSAMB11XR 데이터시트(PDF) 41 Page - Microchip Technology