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MSP432P411VIPZ 데이터시트(PDF) 162 Page - Texas Instruments |
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MSP432P411VIPZ 데이터시트(HTML) 162 Page - Texas Instruments |
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162 / 212 page ![]() Py.x/Mod1/Mod2 PySEL1.x PyDIR.x PyIN.x EN To module From module PyOUT.x 1 0 DVSS DVCC 1 D Pad Logic Direction 0: Input 1: Output PyREN.x 0 1 0 0 1 0 1 1 PySEL0.x 0 1 0 0 1 0 1 1 DVSS DVSS 162 MSP432P4111, MSP432P4011, MSP432P411Y MSP432P401Y, MSP432P411V, MSP432P401V SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018 www.ti.com Submit Documentation Feedback Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated (1) X = Don't care 6.12.8 Port P7 (P7.3) Input/Output With Schmitt Trigger Figure 6-11 shows the port schematic. Table 6-70 lists the settings to select the port functions. Figure 6-11. P7.3 Port Schematic Table 6-70. Port P7 (P7.3) Pin Functions PIN NAME (P7.x) x FUNCTION CONTROL BITS OR SIGNALS (1) P7DIR.x P7SEL1.x P7SEL0.x P7MAPx P7.3/PM_TA0.0 3 P7.3 (I/O) I: 0; O: 1 0 0 X TA0.CCI0A 0 0 1 default TA0.0 1 N/A X 1 0 X N/A 0 1 1 X DVSS 1 |
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