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MSP432P411VIPZ 데이터시트(PDF) 183 Page - Texas Instruments

부품명 MSP432P411VIPZ
상세설명  SimpleLink Mixed-Signal Microcontrollers
PDF  212 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

MSP432P411VIPZ 데이터시트(HTML) 183 Page - Texas Instruments

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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Detailed Description
Copyright © 2017–2018, Texas Instruments Incorporated
(1)
X = Don't care
(2)
Not available on the 64-pin RGC package.
(3)
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
(4)
Setting P7SEL1.x and P7SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
(5)
Setting the CEPD.q bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the C0.q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits
automatically disables the output driver and input buffer for that pin, regardless of the state of the associated CEPD.q bit.
(6)
Setting P7MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger independent of P7SEL1.x and P7SEL0.x
settings.
Table 6-83. Port P7 (P7.4 to P7.7) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
CONTROL BITS OR SIGNALS (1)
P7DIR.x
P7SEL1.x
P7SEL0.x
P7MAPx
P7.4/PM_TA1.4/C0.5/L3
1 (2)
4
P7.4 (I/O)
I: 0; O: 1
0
0
X
TA1.CCI4A
0
0
1
default
TA1.4
1
L31 (3)
X
1
0
X
C0.5 (4) (5) (6)
X
1
1
X
P7.5/PM_TA1.3/C0.4/L3
0 (2)
5
P7.5 (I/O)
I: 0; O: 1
0
0
X
TA1.CCI3A
0
0
1
default
TA1.3
1
L30 (3)
X
1
0
X
C0.4 (4) (5) (6)
X
1
1
X
P7.6/PM_TA1.2/C0.3/L2
9 (2)
6
P7.6 (I/O)
I: 0; O: 1
0
0
X
TA1.CCI2A
0
0
1
default
TA1.2
1
L29 (3)
X
1
0
X
C0.3 (4) (5) (6)
X
1
1
X
P7.7/PM_TA1.1/C0.2/L2
8 (2)
7
P7.7 (I/O)
I: 0; O: 1
0
0
X
TA1.CCI1A
0
0
1
default
TA1.1
1
L28 (3)
X
1
0
X
C0.2 (4) (5) (6)
X
1
1
X



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