| 전자부품 데이터시트 검색엔진 |
|
MSP432P411VIPZ 데이터시트(PDF) 187 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
MSP432P411VIPZ 데이터시트(HTML) 187 Page - Texas Instruments |
|
187 / 212 page ![]() PJ.2/HFXOUT PJSEL0.2 PJDIR.2 PJIN.2 EN To modules DVSS PJOUT.2 1 0 DVSS DVCC 1 D To HFXT XOUT Pad Logic Bus Keeper Direction 0: Input 1: Output PJREN.2 0 1 0 0 1 0 1 1 PJSEL1.2 0 1 0 0 1 0 1 1 DVSS DVSS PJSEL0.3 HFXTBYPASS PJSEL1.3 187 MSP432P4111, MSP432P4011, MSP432P411Y MSP432P401Y, MSP432P411V, MSP432P401V www.ti.com SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018 Submit Documentation Feedback Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated 6.12.23 Port PJ (PJ.2 and PJ.3) Input/Output With Schmitt Trigger Figure 6-23 and Figure 6-22 show the port schematics. Table 6-85 lists the settings to select the port functions. Functional representation only. Figure 6-22. Port PJ (PJ.2) Port Schematic |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |