SLG46110V datasheet(42/82 Pages) DIALOG

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000-0046110-106

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SLG46110

10.6 Programmable Delay Timing Diagram - Edge Detector Output

Note: For delays and widths refer to Table 4.

10.6.1 Programmable Delay Register Settings

Figure 16. Edge Detector Output

Figure 17. Delayed Edge Detector Output

Table 35. Programmable Delay Register Settings

Signal Function

Address

Programmable

delay or filter output

select

reg <485>

0: programmable delay output

1: filter output

Select the edge

mode of

programmable

delay & edge

detector

reg <487:486>

00: Rising Edge Detector

01: Falling Edge Detector

10: Both Edge Detector

11: Both Edge Delay

time1

Edge Detector

Output

Rising Edge Detector

Falling Edge Detector

Both Edge Detector

Both Edge Delay

time1

time1 can be set by register

Delayed Edge

Detector Output

Delayed Rising Edge Detector

Delayed Falling Edge Detector

Delayed Both Edge Detector

Delayed Both Edge Delay

time2

time1 can be set by register

time2 is a fixed value

time1

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