SLG46110V datasheet(36/82 Pages) DIALOG

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000-0046110-106

Page 35 of 81

SLG46110

10.2.2 3-Bit LUT or D Flip Flop Macrocells Used as D Flip Flop Register Settings

Table 28. DFF2 Register Settings

Signal Function

Address

DFF2 or Latch

select

reg <242>

0: DFF function

1: Latch function

DFF2 output select

reg <243>

0: Q output

1: nQ output

DFF2 initial polarity

select

reg <244>

0: Low

1: High

DFF2 rstb/setb

Select

reg <245>

1: setb from matrix out

0: resetb from matrix out

LUT3_0 data

reg <265:258>

LUT3_0 data

LUT3_0 or DFF2

select

reg <282>

0: LUT3_0

1: DFF2

Table 29. DFF3 Register Settings

Signal Function

Address

DFF3 or Latch

Select

reg <250>

0: DFF function

1: Latch function

DFF3 Output Select

reg <251>

0: Q output

1: nQ output

DFF3 rstb/setb

Select

reg <252>

1: setb from matrix out

0: resetb from matrix out

DFF3 initial polarity

select

reg <253>

0: Low

1: High

LUT3_1 data

reg <273:266>

LUT3_1 data

LUT3_1 or DFF3

select

reg <283>

0: LUT3_1

1: DFF3

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