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CS53L32A 데이터시트(PDF) 20 Page - Cirrus Logic

부품명 CS53L32A
상세설명  Low Voltage, Stereo A/D Converter
PDF  40 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS53L32A 데이터시트(HTML) 20 Page - Cirrus Logic

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CS53L32A
20
DS513F1
4.5
MASTER CLOCK DIVIDE
Interface Control Register (address 02h)
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - Disabled
Function:
Divides MCLK by two prior to all other chip circuitry.
4.6
MASTER CLOCK RATIO
Interface Control Register (address 02h)
Access:
R/W in Two Wire Mode and write only in SPI.
Default:
0 - 128x
Function:
Sets the ratio of MCLK to LRCK.
76543
210
RESERVED
MCLKDIV
RATIO1
RATIO0
MASTER
DIF2
DIF1
DIF0
MCLKDIV
MODE
0
Disabled
1
Enabled
Table 4. Master Clock Divide Select
76543
210
RESERVED
MCLKDIV
RATIO1
RATIO0
MASTER
DIF2
DIF1
DIF0
RATIO1,0
MCLK/LRCK RATIO (MCLKDIV=0)
MCLK/LRCK RATIO (MCLKDIV=1)
0
128x
256x
1
192x
384x
2
256x
512x
3
384x
768x
Table 5. MCLK/LRCK Ratios



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