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CS53L32A 데이터시트(PDF) 36 Page - Cirrus Logic |
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CS53L32A 데이터시트(HTML) 36 Page - Cirrus Logic |
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36 / 40 page ![]() CS53L32A 36 DS513F1 LRCK SCLK Left Channel Right Channel SDATA 65432 10 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks Figure 22. CS53L32A Control Port Mode - Serial Audio Format 5 Right Justified, 18-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 36 Cycles per LRCK Period. LRCK SCLK Left Channel Right Channel SDATA 65 4 3 210 987 15 14 13 12 11 10 10 654 3210 98 7 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 Right Justified, 20-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 40 Cycles per LRCK Period. Figure 23. CS53L32A Control Port Mode - Serial Audio Format 6 LRCK SCLK Left Channel Right Channel SDATA +3 +2 +1 LSB +5 +4 MSB -1 -2 -3 -4 -5 +3 +2 +1 LSB +5 +4 MSB -1 -2 -3 -4 I2S, up to 24-Bit Data. Data Valid on Rising Edge of SCLK Figure 24. CS53L32A Stand-Alone Mode - Serial Audio Format 0 (I2S) |
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