CS5530A datasheet(60/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Power Management

Revision 1.1

4.4

Power Management

The

hardware

resources

provided

combined

CS5530A/GX1 based system support a full-featured power

management implementation. The extent to which these

resources are employed depends on the application and

the discretion of the system designer.

Power management resources can be grouped according

to the function they enable or support. The major functions

are as follows:

• CPU Power Management

—On

—Active Idle

— Suspend

— 3 Volt Suspend

—Off

— Save-to-Disk/Save-to-RAM

— Suspend Modulation

• APM Support

• Peripheral Power Management

— Device Idle Timers and Traps

— General Purpose Timers

— ACPI Timer Register

— General Purpose I/O Pins

— Power Management SMI Status Reporting Registers

— Device Power Management Register Programming

Summary

Included in the following subsections are details regarding

the registers used for configuring power management fea-

tures. The majority of these registers are directly accessed

through the PCI configuration register space designated as

Function 0 (F0). However, included in the discussions are

references to F1BAR+Memory Offset 10h. This refers to

the registers accessed through a base address register in

Function 1 (F1) at Index 10h (F1BAR). F1BAR sets the

base address for the SMI status and ACPI timer support

registers as shown in Table 3-11.

4.4.1

CPU Power Management

The three greatest power consumers in a system are the

display, hard drive, and CPU. The power management of

the first two is relatively straightforward and is discussed in

Section 4.4.3 "Peripheral Power Management" on page 67.

CPU power management is supported through several

mechanisms resulting in five defined system power condi-

tions:

• On

• Active Idle

• Suspend

• 3 Volt Suspend

• Off

There are also three derivative power conditions defined:

• Suspend Modulation

— Combination of On and Suspend

• Save-to-Disk

— Off with the ability to return back to the exact system

condition without rebooting

• Save-to-RAM

— Extreme 3 Volt Suspend with only the contents of

RAM still powered

4.4.1.1

System is running and the CPU is actively executing code.

Table 4-11. Base Address Register (F1BAR) for SMI Status and ACPI Timer Support

Bit

Description

F1 Index 10h-13h

Base Address Register — F1BAR (R/W)

Reset Value = 00000000h

This register sets the base address of the memory mapped SMI status and ACPI timer related registers. Bits [7:0] are read only (00h),

indicating a 256-byte memory address range. Refer to Table 5-16 for the SMI status and ACPI timer registers bit formats and reset val-

ues. The upper 16 bytes are always mapped to the ACPI timer, and are always memory mapped.

Note: The ACPI Timer Count Register is accessible through F1BAR+Memory Offset 1Ch and I/O Port 121Ch.

31:8

SMI Status/Power Management Base Address

7:0

Address Range (Read Only)

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