CS5530A datasheet(73/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Power Management

Revision 1.1

Table 4-23. User Defined Device 1 (UDEF1) Idle Timer and Trap Related Registers

Bit

Description

F0 Index 81h

Power Management Enable Register 4 (R/W)

Reset Value = 00h

User Defined Device 1 (UDEF1) Idle Timer Enable: Load timer from UDEF1 Idle Timer Count Register (F0 Index A0h) and

generate an SMI when the timer expires. 0 = Disable; 1 = Enable.

If an access occurs in the programmed address range the timer is reloaded with the programmed count.

UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[4].

F0 Index 82h

Power Management Enable Register 3 (R/W)

Reset Value = 00h

User Defined Device 1 (UDEF1) Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF1 address

programming is at F0 Index C0h (base address register), and CCh (control register).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9].

Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[2].

Index A0h-A1h

User Defined Device 1 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 1 (UDEF1) Idle Timer Count: The idle timer loaded from this register determines when the device

configured as UDEF1 is not in use so that it can be power managed. The 16-bit value programmed here represents the

period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the

count value whenever an access occurs to memory or I/O address space configured at F0 Index C0h (base address regis-

ter) and F0 Index CCh (control register). The timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[4] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[4].

F0 Index C0h-C3h

User Defined Device 1 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 1 (UDEF1) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compara-

tor for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh).

F0 Index CCh

User Defined Device 1 Control Register (R/W)

Reset Value = 00h

Memory or I/O Mapped: User Defined Device 1 is: 0 = I/O; 1 = Memory.

6:0

Mask

If bit 7 = 0 (I/O):

Bit 6

0 = Disable write cycle tracking

1 = Enable write cycle tracking

Bit 5

0 = Disable read cycle tracking

1 = Enable read cycle tracking

Bits 4:0

Mask for address bits A[4:0]

If bit 7 = 1 (M/IO):

Bits 6:0

Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored.

Note: A “1” in a mask bit means that the address bit is ignored for comparison.

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