CS5530A datasheet(87/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Power Management

Revision 1.1

Secondary Hard Disk Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Hard Disk Idle Timer

Count Register (F0 Index ACh)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 83h[7].

Keyboard/Mouse Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the keyboard or

mouse? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 82h[3].

Parallel/Serial Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to either the serial or

parallel ports? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 82h[2].

Floppy Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the

floppy disk? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 82h[1].

Primary Hard Disk Access Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the

primary hard disk? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 82h[0].

Note: This register provides status on the Device Traps to the SMI handler. A bit set here indicates that an access occurred to the

device while the trap was enabled, causing an SMI. Reading this register clears the SMI status bits. A read-only (mirror) version

of this register exists at F0 Index 86h. If the value of the register must be read without clearing the SMI source (and consequently

deasserting SMI), F0 Index 86h may be read instead.

F0 Index F7h

Second Level Power Management Status Register 4 (RO/RC)

Reset Value = 00h

GPIO2 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO2 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 92h[2].

GPIO1 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO1 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 92h[1].

GPIO0 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO0 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 92h[0].

Lid Position (Read Only): This bit maintains the current status of the lid position. If the GPIO6 pin is configured as the lid

switch indicator, this bit reflects the state of the pin.

Lid Switch SMI Status (Read to Clear): SMI was caused by a transition on the GPIO6 (lid switch) pin? 0 = No; 1 = Yes.

For this to happen, the GPIO6 pin must be configured both as an input (F0 Index 90h[6] = 0) and as the lid switch (F0 Index

92h[6] =1).

Codec SDATA_IN SMI Status (Read to Clear): SMI was caused by an AC97 codec producing a positive edge on

SDATA_IN? 0 = No; 1 = Yes.

This is the second level of status is reporting. The top level status is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 80h[5].

RTC Alarm (IRQ8) SMI Status (Read to Clear): SMI was caused by an RTC interrupt? 0 = No; 1 = Yes.

This SMI event can only occur while in 3V Suspend and RTC interrupt occurs.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

ACPI Timer SMI Status (Read to Clear): SMI was caused by an ACPI Timer MSB toggle? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation configuration is at F0 Index 83h[5].

Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI.

This register provides status on several miscellaneous power management events that generate SMIs, as well as the status of

the Lid Switch. Reading this register clears the SMI status bits. A read-only (mirror) version of this register exists at

F0 Index 87h.

Table 4-34. Second Level Pwr Mgmnt SMI Status Reporting Registers (Read to Clear) (Continued)

Bit

Description

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