| 전자부품 데이터시트 검색엔진 |
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MMPF0100Z 데이터시트(PDF) 40 Page - NXP Semiconductors |
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MMPF0100Z 데이터시트(HTML) 40 Page - NXP Semiconductors |
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40 / 128 page ![]() 40 NXP Semiconductors PF0100Z FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS Figure 13. SW1A/B dual phase, SW1C independent mode block diagram In this mode of operation, SW1ALX and SW1BLX nodes operate automatically at 180 ° phase shift from each other and use the same frequency and DVS configured by SW1ABCONF register, while SW1CLX node operate independently using the configuration in the SW1CCONF register. VIN Driver Controller EA Z1 Z2 Internal Compensation SW1AIN SW1ALX SW1FB ISENSE COSW1A CINSW1A LSW1A I2C Interface SW1AB SW1AMODE SW1AFAULT VREF DAC I2C Driver Controller SW1BIN SW1BLX ISENSE COSW1B CINSW1B LSW1B SW1BMODE SW1BFAULT VIN Driver Controller EA Z1 Z2 Internal Compensation SW1CIN SW1CLX SW1CFB ISENSE COSW1C CINSW1C LSW1C EP SW1C SW1CMODE SW1CFAULT VREF DAC I2C VIN |
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