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MMPF0100Z 데이터시트(PDF) 56 Page - NXP Semiconductors

부품명 MMPF0100Z
상세설명  14 channel configurable power management integrated circuit
PDF  128 Pages
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0100Z 데이터시트(HTML) 56 Page - NXP Semiconductors

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NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.5
SW3A/B
SW3A/B are 1.25 A to 2.5 A rated buck regulators, depending on the configuration. Table 29 describes the available switching modes and
Table 30 show the actual configuration options for the SW3xMODE[3:0] bits.
SW3A/B can be configured in various phasing schemes, depending on the desired cost/performance trade-offs. The following
configurations are available:
• A single phase
• A dual phase
• Independent regulators
The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 63 shows the options for the SW3CFG[1:0]
bits.
6.4.4.5.1
SW3A/B single phase
In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 17. This configuration
reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open. Although control is
from SW3A, registers of both regulators, SW3A and SW3B, must be identically set.
Figure 17. SW3A/B single phase block diagram
Table 63. SW3 configuration
SW3_CONFIG[1:0]
Description
00
A/B single phase
01
A/B single phase
10
A/B dual phase
11
A/B independent
Driver
Controller
SW3AIN
SW3ALX
SW3AFB
ISENSE
COSW3A
CINSW3A
LSW3A
I2C
Interface
SW3
SW3AMODE
SW3AFAULT
VIN
Driver
Controller
SW3BIN
SW3BLX
ISENSE
CINSW3B
EP
SW3BMODE
SW3BFAULT
VIN
EA
Z1
Z2
Internal
Compensation
VREF
DAC
I2C
EA
Z1
Z2
Internal
Compensation
VREF
DAC
I2C
SW3BFB



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