56F8014 datasheet(28/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

Table 4-2 Interrupt Vector Table Contents1

Peripheral

Vector

Number

Priority

Level

Vector Base

Address +

Interrupt Function

core

P:$00

Reserved for Reset Overlay2

core

P:$02

Reserved for COP Reset Overlay

core

P:$04

Illegal Instruction

core

P:$06

SW Interrupt 3

core

P:$08

HW Stack Overflow

core

P:$0A

Misaligned Long Word Access

core

1-3

P:$0C

EOnCE Step Counter

core

1-3

P:$0E

EOnCE Breakpoint Unit 0

core

1-3

P:$10

EOnCE Trace Buffer

core

1-3

P:$12

EOnCE Transmit Register Empty

core

1-3

P:$14

EOnCE Receive Register Full

core

P:$16

SW Interrupt 2

core

P:$18

SW Interrupt 1

core

P:$1A

SW Interrupt 0

Reserved

0-2

P:$20

Power Sense

OCCS

0-2

P:$22

PLL Lock, Loss of Clock Reference Interrupt

0-2

P:$24

FM Access Error Interrupt

0-2

P:$26

FM Command Complete

0-2

P:$28

FM Command, data and address Buffers Empty

Reserved

GPIOD

0-2

P:$2C

GPIOD

GPIOC

0-2

P:$2E

GPIOC

GPIOB

0-2

P:$30

GPIOB

GPIOA

0-2

P:$32

GPIOA

SPI

0-2

P:$34

SPI Receiver Full / Error

SPI

0-2

P:$36

SPI Transmitter Empty

SCI

0-2

P:$38

SCI Transmitter Empty

SCI

0-2

P:$3A

SCI Transmitter Idle

SCI

0-2

P:$3C

SCI Reserved

SCI

0-2

P:$3E

SCI Receiver Error

SCI

0-2

P:$40

SCI Receiver Full

33, 34

Reserved

I2C

0-2

P:$46

I2C

Timer

0-2

P:$48

Timer Channel 0

Timer

0-2

P:$4A

Timer Channel 1

(Continues next page)

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