56F8014 datasheet(8/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

Figure 1-1 System Bus Interfaces

Note:

Flash memories are encapsulated within the Flash Interface Unit (FIU). Flash control is accomplished

by the I/O to the FIU over the peripheral bus, while reads and writes are completed between the core

and the Flash memories.

Note:

The primary data RAM port is 32 bits wide. Other data ports are

16 bits.

56800E

Program

Flash

Data /

Program

RAM

IPBus

Bridge

Flash

Interface

Unit

CHIP

TAP

Controller

TAP

Linking

Module

primary data read port

secondary data read port

Program reads

can be done on

secondary port

of data memory

Program writes

can be done on

primary port of

data memory

NOTE: All Flash reads and writes are routed through

the Flash interface units, which encapsulate the Flash

memories. This is not shown for clarity’s sake.

JTAG / EOnCE

pdb_m[15:0]

pab[20:0]

xdb2_m[15:0]

xab2[23:0]

cdbw[31:0]

pdb_m[23:0]

cdbr_m[31:0]

IPBus

To Flash

Control Logic

External

JTAG Port

GPIO

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