56F8014 datasheet(69/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

6.3.7

CLKO Select Register (SIM_CLKOUT)

The CLKO select register can be used to multiplex out selected clocks generated inside the clock

generation and SIM modules. All functionality is for test purposes only and is subject to

unspecified latencies. Glitches may be produced when the clock is enabled or switched.

The lower four bits of the GPIO A register can function as GPIO, PWM, or as additional clock output

signals. GPIO has priority and is enabled/disabled via the GPIOA_PEREN. If GPIOA[3:0] are

programmed to operate as peripheral outputs, then the choice between PWM and additional clock outputs

is done here in the CLKOUT. The default state is for the peripheral function of GPIOA[3:0] to be

programmed as PWM. This can be changed by altering PWM3 through PWM0.

Figure 6-8 CLKO Select Register (SIM_CLKOUT)

6.3.7.1

Reserved—Bits 15–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.3.7.2

PWM3—Bit 9

•

0 = Peripheral output function of GPIOA[3] is defined to be PWM3

•

1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock

6.3.7.3

PWM2—Bit 8

•

0 = Peripheral output function of GPIOA[2] is defined to be PWM2

•

1 = Peripheral output function of GPIOA[2] is defined to be the system clock

6.3.7.4

PWM1—Bit 7

•

0 = Peripheral output function of GPIOA[1] is defined to be PWM1

•

1 = Peripheral output function of GPIOA[1] is defined to be two times the rate of the system clock

6.3.7.5

PWM0—Bit 6

•

0 = Peripheral output function of GPIOA[0] is defined to be PWM0

•

1 = Peripheral output function of GPIOA[0] is defined to be three times the rate of the system clock

6.3.7.6

Clockout Disable (CLKDIS)—Bit 5

•

0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL

•

1 = CLKOUT is 0

Base + $A

Read

PWM

PWM1PWM0

CLK

DIS

CLKOSEL

Write

RESET

0000

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