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DSP56857 데이터시트(PDF) 215 Page - Freescale Semiconductor, Inc

부품명 DSP56857
상세설명  Digitial Signal Controller
PDF  662 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 데이터시트(HTML) 215 Page - Freescale Semiconductor, Inc

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Interrupts
Overview, Rev. 4
Freescale Semiconductor
8-37
this newly requested interrupt. The core will latch IPIC_LEVEL and it will be driven back to the
Interrupt Controller as new values on the SR_REG[9:8] pins.
When the 56800E core recognizes the assertion of the interrupt pin, it will deassert PIC_EN
which tells the Interrupt Controller to drive VAB with the address corresponding to the highest
priority interrupt request in order to start the interrupt service routine. When the 56800E core
asserts the IACK signal, the Interrupt Controller will deassert the interrupt signal to the core. The
controller will not reassert the interrupt signal until PIC_EN is asserted by the 56800E core.
Figure 8-26. Interrupt Handshake Timing
8.11.2 Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception
to be serviced. The following tables define the nesting requirements for each priority level.
Table 8-4. Interrupt Mask Bit Definition
SR
SR
Exceptions
Permitted
Exceptions
Masked
0
0
Priorities 0, 1, 2, 3
None
0
1
Priorities 1, 2, 3
Priority 0
1
0
Priorities 2,3
Priorities 0, 1
1
1
Priority 3
Priorities 0, 1, 2
VAB
CLK
INT
PIC_EN
SR_REG[9:8]
00
01
IACK
IPIC_LEVEL
00
01
01
00
01
v0
v0
IRQ_B



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