DSP56857 datasheet(36/662 Pages) FREESCALE

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5685x Family Description

5685X Digital Signal Controller User Manual, Rev. 4

1-4

Freescale Semiconductor

With the exception of the 56857, the balance of the 5685x family of devices supports program

execution from either internal or external memories. Two data operands can be accessed from the

on-chip Data RAM per instruction cycle. The 5685x family also provides two external dedicated

interrupt lines, and up to 47-General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration.

All devices, except the 857, support program execution from external memory. The 56800E core

can access two data operands from the on-chip Data RAM per instruction cycle.

These controllers also provides a full set of standard programmable peripherals that include an

8-bit Host Interface (HI8), up to two Enhanced Synchronous Serial Interfaces (ESSI), one Serial

Peripheral Interface (SPI), two Serial Communications Interfaces (SCI), and one Quad Timer

(TMR). When primary functions of each of the peripheries (HI8, TMR, ESSI, SPI, SCI I/O and

four chip selects) are not required, they can be used as General Purpose Input/Outputs (GPIOs).

Please see Section 1.3 for details on each of the 5685x family of devices.

1.2.1 5685x Key Family Features

1.2.1.1 The 56853

•

Supports program execution from either internal or external memories

•

Provides two external dedicated interrupt lines

•

Provides up to 41-General Purpose Input/Output (GPIO) lines, depending on peripheral

configuration

•

Includes 12K words of Program RAM

•

Includes 4K words of Data RAM

•

Includes 1K words of Boot ROM

•

Provides a full set of standard programmable peripherals including:

— eight-bit Host Interface (HI8)

— one Enhanced Synchronous Serial Interface (ESSI)

— one Serial Peripheral Interface (SPI)

— two Serial Communications Interfaces (SCIs)

— one Quad Timer (TMR)

— one, 6-channel Direct Memory Access (DMA)

The HI8, ESSI, SPI, SCI, four chip selects and TMR can be used as General Purpose

Input/Outputs (GPIOs) if its primary function is not required.

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