DSP56857 datasheet(66/662 Pages) FREESCALE

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Peripheral Descriptions

5685X Digital Signal Controller User Manual, Rev. 4

1-34

Freescale Semiconductor

It provides simple, inexpensive, and speed-independent access to the 56800E core for

sophisticated debugging and economical system development. The JTAG/EOnCE port provides

access to the EOnCE module. The JTAG/EOnCE port retains debug control without sacrificing

other accessible on-chip resources through the 5685x devices to its target system.

1.12.12 Six-Channel DMA Controller

•

The DMA operates independently of the CPU.

•

The 5685x DMA includes six channels. The DMA can handle the contexts of six

independent block transfers.

•

The DMA Controller has access to 33 percent of the system bus traffic. This one-quarter

duty cycle is governed by the 5685x System Bus Controllers.

•

Each channel has independently programmable peripheral selection.

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Each channel’s source and destination address registers has configurable indices.

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For each memory fetch and put, the address may remain constant, be post incremented, or

post decremented.

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Each read or write transfer may be initiated by selected events: specified peripheral

requests or direct CPU triggering may launch a new DMA transaction.

— Upon completion of a block transfer, each DMA channel may send an interrupt to the

CPU.

— The DMA includes a circular queue operational mode providing continuous DMA

operation with no additional processor intervention.

1.12.13 Peripheral Interrupts/Interrupt Controller

The peripherals on the 5685x use the ITCN module to interface to the interrupt signal found on

the 56800E core. Each peripheral has its own interrupt vector, often more than one interrupt

vector for each peripheral, and can selectively be enabled or disabled via the IPR registers. The

Interrupt Controller (ITCN) module design includes these distinctive features:

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Programmable priority levels for each IRQ

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Two programmable Fast Interrupts

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Notification to SIM module to restart clocks out of Wait and Stop modes

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