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DSP56857 데이터시트(PDF) 47 Page - Freescale Semiconductor, Inc

부품명 DSP56857
상세설명  Digitial Signal Controller
PDF  662 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 데이터시트(HTML) 47 Page - Freescale Semiconductor, Inc

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56800E Core Description
5685X Overview, Rev. 4
Freescale Semiconductor
1-15
Complete architecture includes these components:
•
56800E core
•
On-chip program memory
•
On-chip data memory
•
On-chip peripherals
•
IPBus peripheral interface
•
External bus interface
Some 56800E devices might not implement an external bus interface. Regardless of the
implementation, all peripherals communicate with the 56800E core via the IPBus interface. The
IPBus interface standard connects the main data address bus XAB1, CDBR, and CDBW
unidirectional data buses to the corresponding bus interfaces on the peripheral devices. The
program memory buses are not connected to peripherals.
1.4.4 56800E Core Block Diagram
The 56800E core is composed of several independent functional units. The program controller,
Address Generation Unit (AGU), and data Arithmetic Logic Unit (ALU) contain their own
register sets and control logic, allowing them to operate independently and in parallel, which
increases throughput. There is also an independent bit-manipulation unit enabling efficient
bit-manipulation operations. Each functional unit interfaces with the other units, memory, and the
memory-mapped peripherals over the core’s internal address and data buses. A block diagram of
the 56800E core architecture is shown in Figure 1-7.



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