DSP56857 datasheet(295/662 Pages) FREESCALE

295 / 662 page

SPI Register Descriptions (SPI_BASE = $1FFFE8)

Serial Peripheral Interface (SPI), Rev. 4

Freescale Semiconductor

11-25

11.11.1.10 SPI Transmit Interrupt Enable (SPTIE)—Bit 4

This read/write bit enables interrupt requests generated by the SPTE bit. SPTE is set when a full

data length transfers from the SPI Data Transmit Register (SPDTR) to the Shift register. The SPI

Transmitter Interrupt Enable (SPTIE) bit enables the SPTE flag to generate transmitter interrupt

requests, provided the SPI is enabled (SPE = 1). The clearing mechanism for the SPTE flag is

always just a write to the SPDTR.

•

0 = SPTE interrupt requests disabled

•

1= SPTE interrupt requests enabled

11.11.1.11 SPI Receiver Full (SPRF)—Bit 3

This read-only flag is set each time full length data transfers from the Shift register to the SPI

Data Receive Register (SPDRR). SPRF generates an interrupt request if the SPRIE bit in the SPI

Status and Control Register (SPSCR) is set also. This bit may not be cleared.

•

0 = Data Receive register not full

•

1 = Data Receive register full

11.11.1.12 Overflow (OVRF)—Bit 2

This read-only flag is set if software does not read the data in the SPI Data Receive Register

(SPDRR) before the next full data enters the Shift register. In an overflow condition, the data

already in the SPDRR is unaffected, and the data shifted in last is lost. Clear the OVRF bit by

reading the SPI Status and Control Register (SPDSCR) with OVRF set and then reading the

SPDRR. This bit may be cleared using the proper software sequence.

•

0 = No overflow

•

1 = Overflow

11.11.1.13 Mode Fault (MODF)—Bit 1

This read-only flag is set in a slave SPI if the SS pin goes high during a transmission with the

MODFEN bit set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with

the MODFEN bit set. Clear the MODF bit by writing one to the MODF bit when it is set. The

delayed bit results in only the OVRF interrupt being enabled by the ERRIE bit. This enabling

generates Receiver/Error Interrupt requests.

•0 = SS pin at appropriate logic level

•1 = SS pin at inappropriate logic level

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