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DSP56857 데이터시트(PDF) 304 Page - Freescale Semiconductor, Inc |
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DSP56857 데이터시트(HTML) 304 Page - Freescale Semiconductor, Inc |
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304 / 662 page ![]() Signal Descriptions 5685X Digital Signal Controller User Manual, Rev. 4 12-4 Freescale Semiconductor 12.3 Signal Descriptions 12.3.1 Signal Properties 12.3.2 External Signals Descriptions Three to six signals are required for ESSI operation, depending on the selected operation mode. The function of the I/O pins for the ESSI is determined by a number of control bits. Table 12-2 lists the controls affecting this and the resulting pin definitions. The Serial Transmit Data (STD) signal and Serial Control (SC0 and SC1) signals are fully synchronized to the clock if they are programmed as transmit data signals. Table 12-3 further clarifies the possible configuration of the SC0 and SC1 pins during synchronous modes when they are not being used as transmit data pins. In addition to the functional configuration of the I/O pins, the direction of clocks and frame syncs can be configured. The source of the transmit and receive clocks used by ESSI is determined by three control bits, illustrated in Table 12-1. The source of the receive and transmit frame syncs is determined by three control bits, illustrated in Table 12-3. Table 12-1. Signal Properties Name Type Function Reset State Notes SCK I/O ESSI Transmit Clock Input Controlled by Reset State of SCKD bit in SCR4 register SC2 I/O ESSI Transmit Frame Sync Input Controlled by Reset State of SCD2 bit in SCR4 register SC0 I/O ESSI Receive Clock Input Controlled by Reset State of SCD0 bit in STR4 register SC1 I/O ESSI Receive Frame Sync Input Controlled by Reset State of SCD1 bit in STR4 register STD Output ESSI Transmit Data Hi-Z Since ESSIEN bit is SCR2 register is reset to 0 SRD Input ESSI Receive Data — — |
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