DSP56857 datasheet(322/662 Pages) FREESCALE

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Functional Description

5685X Digital Signal Controller User Manual, Rev. 4

12-22

Freescale Semiconductor

Figure 12-8. Network Mode Receive Timing with Mask Register

Table 12-11. Notes for Receive Timing with Mask Register in Figure 12-33

Note

Source

Signal

Destination

Signal

Description

6—

—

Example of a five time slot frame, receive data from time slots 0 and 2.

The receive hardware will only obtain data on the SRD pin when the

RSMn bit is set to one.

7SC1

—

Example with bit length frame sync and standard timing (RFSI=0,

RFSL=1, and REFS=0). Frame timing begins with the rising edge of

SC1.

8SRD

RXSR

Data on the SRD pin is sampled on the falling edge of SC0 and shifted

into the RXSR register.

RXSR

SRX

At the word clock, the data in the RXSR register is transferred to the

SRX register, for enabled time slots.

RDR Status Flag

and Receive

Interrupt

—

This flag is set for each word clock, or time slot, where the RSMn bit is

set, indicating data is available to be processed. The software must

keep track of the time slots as they occur so it knows which data it is

processing.

When the receive interrupts are enabled (RIE=1) an interrupt will be

generated when this status flag is set. The software reads the SRX

Section 12.13 provides a complete description of the interrupt process.

TS 0

TS 1

TS 2

TS 3

TS 4

TS 0

RSM[0]

RSM[1]

RSM[2]

RSM[3]

RSM[4]

RSM[0]

Time Slot

SC0

Internal Word Clock

SC1

RSMn Bits Usage

RTSCNT Field of SFSR Register

SRD

RXSR Register

SRX Register

RDR Status Bit / Interrupt

Valid

Indefinite transition depends on SW interrupt processing

Invalid

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